1. Field of the Invention
The present invention relates to a method for performing a test on an integrated circuit with built-in self-test features. Further the present invention relates to an integrated circuit with built-in self-test features.
2. Description of the Related Art
Integrated semiconductor circuits include a plurality of functional units. During the production said functional units have to be tested. For that purpose current integrated circuits have built-in self-test features, which are able to test the functional units in order to detect defects on the circuit. The results of said built-in self-test features have to be accessed by an external test system.
FIG. 3 shows a schematic diagram of an integrated circuit 70 with a functional unit 20 and said built-in self-test features according to the prior art. The integrated circuit 70 comprises an input terminal 12 and an output terminal 14. The input terminal 12 receives an external clock from the test system. The output terminal 14 sends a failure signal to the test system, if a defect is detected. Further the integrated circuit 70 comprises a clock distributor 16, a stimuli logic 18, the functional unit 20 and a comparator 22. The built-in self-test features are formed by the clock distributor 16, the stimuli logic 18 and the comparator 22.
The clock distributor 16 includes a PLL multiplier to transform the external clock from the test system into a faster internal clock within the integrated circuit. The stimuli logic 18 generates test patterns applied to the functional unit 20. The comparator 22 compares the response from the functional unit 20 with an expected test pattern. If a defect occurs within the functional unit 20 under test, then the response pattern does not match the expected value in the comparator 22 and the signal on the output terminal 14 will be set to a logic value indicating that a defect is detected. Said logic value on the output terminal 14 will be set back as soon as the built-in self-test features step further to the next test pattern. The counting of the pulses of the internal clock from the start of the pattern to the event of a failure signal allows the determination of stimuli and expected pattern at that time the failure occurs. In the case the functional unit is memory array, stimuli is the address to the array and the expected pattern is the data read from the memory array. On the basis of the failure addresses, a bit failure map can be built. These bit failure maps are required as an input for a physical analysis.
The test system is able to recognize every failure, if the integrated circuit and the test system work with a similar clock. However, if the internal clock within the integrated circuit is much faster than the clock of the test system, the integrated circuit cannot be tested at its maximum speed.
The article “Prototype testing of high-speed CMOS digital circuits” by Volker Schindler, ISCAS'96, Vol. 4, pp. 160-163, describes built-in self-test features, which may be switched between the proper integrated circuit under test and the test system. The test system is provided to determine the maximum frequency of the integrated circuit.
In the article “Method for performing a critical path test of a fast digital circuit on slow test equipment” by Tommaso Bacigalupo, IPCOM000018571D, a two-step-method is disclosed. Said two-step-method allows a high-speed test of an integrated circuit with a low-speed test system. In a first step the test runs at the full speed with an internal clock up to a point, where the timing violation is expected to occur. In a second step the test runs at a lower speed with an external clock.
U.S. Pat. No. 5,381,087 describes a high-speed LSI chip to be tested and evaluated by a low-speed semiconductor tester. A selector circuit switches between the oscillator of the high-speed LSI chip and the low-speed semiconductor tester in dependence of the frequency, which is required to activate high-speed LSI chip.
In EP 0 485 238 A2 an integrated circuit semiconductor chip for the detection of the required operational speed is disclosed. An oscillator circuit, a counter and a comparator are formed on the semiconductor chip. A tester provides timing, control and a display. If the speed of the operation is very high, then the speed is divided.